1. Field of the Invention
The present invention relates to a semiconductor device in which an integrated circuit is formed on one main surface (e.g., front surface), in which a bump electrode is formed on another main surface (e.g., rear surface) that is on the opposite side of the one main surface with a semiconductor substrate sandwiched therebetween, and in which a penetrating electrode adapted to electrically connect the bump electrode and integrated circuit is formed in such a manner as to penetrate the semiconductor substrate in the thickness direction. The present invention also relates to a penetrating electrode testing method for electrically testing such a penetrating electrode for connection at both ends thereof.
2. Description of the Related Art
The three-dimensional integration technique is known that is designed to stack a plurality of semiconductor substrates, each having an integrated circuit formed thereon, one on top of another. The progress of this technique owes much to the technical development of a contact pressure type microprotruding electrode called microbump, the formation technique of a penetrating electrode that penetrates a semiconductor in the thickness direction, the reduction in thickness of semiconductors and the progress of handling and other techniques.
In order to form a three-dimensional integrated circuit, chips, each having an integrated circuit formed on its front surface and bump electrode formed on its rear surface, are generally stacked one on top of another on a semiconductor substrate serving as a mother substrate. At this time, it is known to mount, for example, a boundary scan test circuit to ensure connection between a bump electrode and pad and between bump electrodes on different substrates.
The condition of each of the chips to be stacked or the formation of the penetrating electrode in a wafer condition must be tested. That is, it is necessary to check the continuity in the substrate between the bump electrode used for external connection and the penetrating electrode.
As for a short failure of the penetrating electrode, a proposal for an invention has been already made for a circuit that allows for detection of such a failure through ordinary surface wafer testing (refer, for example, to Japanese Patent Laid-Open No. 2008-96312, hereinafter as Patent Document 1)